1. Field of the Invention
The invention relates generally to a method of manufacturing a memory device and, more particularly, to a method of manufacturing a flash memory device, wherein the profile of a polysilicon layer for a floating gate is formed negatively.
2. Discussion of Related Art
In a flash memory device of 70 nm or less, an isolation film formation process is described as follows.
A tunnel oxide film, a first polysilicon layer for a floating gate, a nitride film, and a SiON layer are sequentially formed on a semiconductor substrate. The SiON layer, the nitride film, the first polysilicon layer, the tunnel oxide film, and a portion of the semiconductor substrate are sequentially etched by photolithography and etch processes employing a mask, thereby forming trench.
A sidewall oxide film is formed on surfaces of the trench and a high-density plasma (HDP) oxide film is then formed on the entire structure. The HDP oxide film is polished until a top surface of the nitride film is exposed, thereby forming an isolation film. The nitride film is stripped. At this time, when the first polysilicon layer is etched, the profile of the first polysilicon layer has a positive slope form. The profile of the first polysilicon layer has a clearer positive slope form by sidewall oxide film and HDP oxide film formation process (i.e., a subsequent process).
A second polysilicon layer for a floating gate is formed on the entire structure. The second polysilicon layer is etched by means of photolithography and etch processes employing a mask, thereby forming a floating gate including the first polysilicon layer and the second polysilicon layer. A dielectric layer and a conductive layer for a control gate are then formed on the entire structure. The conductive layer, the dielectric layer, and the second and first polysilicon layers are patterned to form the control gate vertical to the isolation film.
If the gates are formed as described above, however, a portion of the first polysilicon layer extends below the isolation film when they are etched. Accordingly, the first polysilicon layer remains at both sidewall edges of the isolation film due to etch-stop by the isolation film when the gates are etched. As a result, the floating gates adjacent in the direction of the isolation film are interconnected. Accordingly, failure is generated and the reliability of the device is lowered.
Meanwhile, since the first polysilicon layer has a positive profile form, the critical dimension (CD) of the active region is increased. As the pattern becomes finer, the margin of the photo process is shortened and a phenomenon in which the pattern collapses or is twisted upon etch is generated.